1. Field of the Invention
The present invention relates to electronic circuitry suitable for use in a semiconductor integrated circuit. More specifically, this invention relates to a driver circuit for high speed digital signal transmission on a transmission line.
2. Description of the Related Art
Digital computers and the like often include a plurality of VLSI circuits which are interconnected for binary communications by single element or multisegment transmission lines (collectively referred to herein as "transmission lines"). Transmission lines include parallel conductors, coaxial cable, and, conventionally, electrically conductive traces formed on a suitable substrate, such as a printed circuit board. A transmission line, whatever its form, has a characteristic impedance such that a wave traveling along the line has a ratio of voltage to current equal to the characteristic impedance. Typically, printed circuit board traces and coaxial lines have impedances in the range of 50 to 100 ohms. When used with high frequency (or short rise/fall time) signals, it is important to "match" the load to the characteristic impedance of the line since a transmission line terminated with a load equal to its characteristic impedance (resistance) will transfer an applied pulse to the termination without reflection thus maximizing signal/power transfer to and from an attached load. Accordingly, standard practice terminates the opposite ends of the transmission line in their characteristic impedance, and VLSI circuits and other devices attached to the transmission line are series stub-terminated in order to match the impedance of an attached signal driver or receiver to the characteristic impedance of the transmission line. An output driver (sometimes called an "output buffer" or "signal line driver") is an electronic circuit that furnishes one or more output signals at voltage/current levels suitable to drive the transmission line to permit interfacing of the various VLSI components.
Special problems arise, however, when trying to send high-speed digital signals through transmission lines such as capacitive loading of the fast signals, common mode interference pickup, and signal reflections from impedance mismatching. As motherboards (a printed circuit board containing multiple edge connectors to accept individual circuit cards that make up the logic circuit) increase in complexity, and data and control bus clock speeds continue to increase, there is a corresponding increase in the capacitive loading on digital signal output drivers principally due to stray wiring capacitance and the input capacitance of the driving chips themselves. These all contribute to the load on the output driver. Consequently, in order to make a fast transition between logic states, the output driver must sink or source a large current into the transmission line in order to provide an output signal having logic high and logic low signals within their specified voltage ranges.
Conventional interface specifications between integrated circuits have resulted in manufacturers designing special circuitry to accommodate, or satisfy, these interface standards. However, as the number of intercard connections increases, and as backplane, or motherboard, complexity and bus speeds increase, capacitive loading for signal line drivers increases proportionally, such that conventional interface drivers can no longer meet the specified high and low logic signal voltage levels. Recognizing this problem, the Electronic Industry Association ("EIA") periodically releases new standards reducing the voltage swing required between high and low logic levels in order, thus somewhat mitigating the power requirements needed to accommodate the increased loading due to the inherent capacitance of the transmission line (for example, see EIA/JEDEC Standard No. 8-8), entitled "Stub Series Terminated Logic for 3.3 Volts (SSTL.sub.-- 3), A 3.3 V voltage based interface standard for digital integrated circuits"). In view of the relatively limited voltage swings associated with these reduced voltage standards, the voltage ranges corresponding to the high logic level voltage and the low logic level voltages are necessarily narrower.
A line signal driver capable of accommodating the high capacitive loads of high speed, multi-device transmission lines is shown in prior art FIG. 1. Multiple signal Gunning Transfer Logic (GTL) drivers 1 are shown attached to a transmission line 2 having a characteristic impedance of 50 ohms. The transmission line 2 is end terminated at its opposite ends with 50 ohm resistors 3 and 4 and lumped capacitances 5 and 6 are the equivalent of the stray wire and input capacitances which comprise the capacitive loading of the transmission line 2. Each of the GTL drivers 1 is stub terminated with a resistor 7 to match the characteristic impedance of transmission line 2. When all of the GTL drivers 1 are off, the transmission line 2 is pulled up to the 1.5 positive supply voltage shown by the impedance matching pullup resistors 3 and 4. However, when at least one GTL driver 1 is turned on, the voltage in transmission line 2 is reduced since the stub series resistors 7 create a voltage divider with pullup resistors 3 and 4. The new transmission line voltage is 1.5 volts times the ratio of the combined resistance of the stub-series resistors 7 associated with drivers currently ON, to the sum of the combined resistance of the stub termination resistors 7 of those drivers 1 that are turned ON and the pullup resistors 3 and 4. It is apparent that as increasing numbers of drivers 1 are turned ON, the combined resistance of the stub termination resistors becomes very small, thus dragging the nominal voltage of the transmission line 2 to a low value. Accordingly, as additional drivers turn on it becomes very difficult to distinguish the logic low level voltage from the nominal voltage level of the transmission line, the two voltages approaching ground, or zero volts, as the number of GTL drivers 1 that are turned on becomes large.
Output-stage current transients resulting from simultaneous biasing of the CMOS transistors, and voltage spikes, or ground bounce, associated with dumping large doses of current to ground when driving capacitive loads may still be introduced onto the transmission line 2. Even though the voltage is reduced to 1.5 volts in the transmission interface shown in FIG. 1, if the output stage of the amplifier (not shown) driving each of the GTL drivers 1 is a CMOS in a "totem-pole" output configuration with the pulldown transistor terminating to ground, substantial current may still be switched, and ground current noise introduced onto transmission line 2 from each driver 1 as it switches ON and OFF.
Elimination of ground bounce in an output driver is described by Campbell et al., in related issued U.S. Pat. No. 5,430,404. Campbell uses a charge rate control circuit for charging the gates of its pullup and pulldown output transistors at a first gate voltage for an initially rapid output transition rate, followed by a second gate voltage for a slower transition rate, thus minimizing overshoot and ringing of the output signal, as well as bounce on the voltage supply lines. Also, the output transistors include a bulk potential control circuit to change the voltage of the semiconductor bulk in which the FET is disposed resulting in a reduction of noise associated with ground bounce on the voltage supply lines.
In another related application by Go Ang et al., U.S. Pat. No. 5,028,818, a ground-bounce limiting circuit comprising a predriver circuit and a non-linear Miller capacitor between the drain and gate of an output driver is used to limit ground bounce. The Miller capacitor provides non-linear feedback between the gate and drain of the output driver to control the time-ramping of the output current of the output transistor.
Both the Campbell and Ang circuits describe reducing the generation of ground bounce noise by controlling the discharge rate of the pulldown output transistor. Neither circuit, however, describes protecting the driver from power supply or ground noise. Moreover, neither describes providing additional drive current during logic state transitions to provide high speed or high frequency signal capability on a high capacitance transmission line. Accordingly, there is a need for a signal line driver capable of providing stable high/low voltages at specified high/low logic states in a low voltage transmission line system comprising a transmission line having a specified null voltage value, and a plurality of signal line drivers. There is a further need for a signal line driver providing high frequency digital signal generation on a transmission line having a high inherent capacitance without substantial ground bounce, and capable of rejecting power supply noise.